Qwenputer: a deterministic RISC-V CPU compiled into Qwen3.5 4B weights, using Gated DeltaNet layers as RAM
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Divyansh Agrawal compiled a RISC-V CPU into a stock Qwen 3.5 4B, using the model's Gated DeltaNet layers as exact RAM so it runs arithmetic, C and MicroPython inside forward passes with no external tool. Weights are on Hugging Face and ModelScope and code on GitHub. The post (Oct 22) reached the HN front page today; follow-ups explore hidden reasoning in RNN state.
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- hn post ↗ · 195 points, 43 comments · observed 10/29/2026, 4:09:24 AM
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